Catherine TASTE

Responsible for interface with semiconductor suppliers for the development of a family of devices – ASICs ASSP and MCUs with optimized silicon partitioning for the future generation of Electronic Power Steering products. Investigates and identifies market trends, cost drivers and best silicon solutions to support platform strategy. Insures coordination with system teams in UK to develop a comprehensive set of specifications.

Responsible for communication and interface with customer. Managed schedule, deliverables, cost, risks, status and reporting of complex ASIC and ASSP projects from feasibility to production. Interacts directly with the projects leaders developing silicon and software, and with international multicultural teams e.g. Technology, Test, Packaging, Product engineering, Reliability & Quality, Sales and Marketing departments. Responsible for change management and approval as well as lessons learned creation.

• Program Manager in the Embedded Power group for automotive applications. Led the developments of SBCs/LIN,CAN transceivers ASSP using BiCDMOS processes from initial concept to production. Coordinated multi-sites team Front End and Back End, implemented risk analysis and risk management, established schedule, managed budget, resources and deliverables. Interface with skate-holders. • Overall Project Leader for the development of a new Power Copper BiCDMOS Technology for automotive applications. Coordinate

Led the design development of Motor Driver ICs using 1.2µ BiCDMOS from initial concept to customer samples (first silicon fully functional!). Responsibility included circuit design, top-level simulations using CADENCE platform, data base management, layout and verification supervision, product engineering, test and reliability support. Insured coordination between vendors (US, Europe and Japan) and drive teams, managed schedules, resources and deliverables.

•Computer Peripheral Group •Sr. Analog Design Engineer 1991- 1993 New Product Development Group Design Engineer 1986 - 1991 •Engineering Support Group Analog Engineer 1983 –1986 Worked on mixed-mode ASICs design, analysis and simulations for Disk Drive read Channel applications. Designed and developed a new series of high frequency semi-custom arrays.

CMOS design - level I and II

Microelectronics Analog Design - digital design Semiconductor Technologies ( Bipolar / CMOS) CAD - transistor modeling Failure Analysis Thin film and thick film technologies

E.E.A Electronics. Electrotechnics and Automation