Padmaprasad Boopal
Angestellt, Senior Consultant - FPGA Design, ALTEN SW GmbH
Heimsheim, Deutschland
Über mich
I am someone who enjoys work and is passionate about what I am doing. I am a person who assumes responsibility for my actions and one who can be trusted with challenging tasks. I strive to find innovative solutions and always look for ways to improve. I believe in working and growing as a team & also a strong individual contributor My strong passion for digital design, developed while working with a start-up in India and since then I have designed, developed, and successfully delivered digital FPGA designs ranging from simple to complex and extraordinarily complex. My experience also encompasses strong managerial skills with a proven record of technical project management, team building and mentoring. Having mostly worked in the service industry, I feel my strongest asset is development of everlasting professional relationship with the management, clients, and resources Specialties: RTL FPGA, Digital Logic Design, Matlab, SoC - Hardware-Software Co-Design, Firmware development
Werdegang
Berufserfahrung von Padmaprasad Boopal
Bis heute 7 Jahre und 3 Monate, seit Apr. 2017
Senior Consultant - FPGA Design
ALTEN SW GmbH
an individual contributor working on FPGA datapath designs for ATEs. Involved in design and implementation of functional blocks in Verilog/System Verilog, functional verifcation and hardware validation. Firmware development.
3 Jahre und 7 Monate, Aug. 2013 - Feb. 2017
Specilaist (FPGA Design)
Robert Bosch Engineering and Business Solutions LimitedFPGA Development Module design and development in VHDL Design responsible Automated Test bench environment creation Functional verification STA and Timing Closure Hardware low level tests and on-board validation
ASIC RTL coding ASIC - FPGA porting and Validation SoC integration
9 Monate, Okt. 2011 - Juni 2012
Senior Engineer - Digital Design
Exor India Pvt Ltd
Lattice FPGA based System on Chip development for Human Machine Interface Panels. ARM AMBA Bus Architecture - APB, AHB, AXI RTL design in VHDL and functional verification
1 Jahr und 9 Monate, Okt. 2007 - Juni 2009
Senior Design Engineer
Tata Elxsi
Design of FPGA based Electronics Control Unit for Automotive. Matlab modelling for Hybrid Vehicles
2 Jahre und 4 Monate, Mai 2005 - Aug. 2007
Hardware Design Engineer
VDesign Technologies
Design and development of FPGA based hardware designs for Avionics.
Ausbildung von Padmaprasad Boopal
2 Jahre und 2 Monate, Aug. 2009 - Sep. 2011
Electrical engineering
Linkoping university, Sweden
System on Chip, Digital CMOS Design, FPGA Design, VHDL/Verilog, CAD, RF Electronics
Sprachen
Englisch
Fließend
Deutsch
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