Alessandro Uber

Angestellt, Senior Specialist Design Flow and Methodology, Intel Deutschland GmbH

Munich, Deutschland

Fähigkeiten und Kenntnisse

Digital back-end design
design for testability
RTL (VHDL/Verilog) coding
floorplanning
hierarchical design planning
low-power design optimization
timing closure
design closure
physical verifications
formal verifications
Magma
Synopsys
Cadence
Mentor.

Werdegang

Berufserfahrung von Alessandro Uber

  • Bis heute 13 Jahre und 4 Monate, seit März 2011

    Senior Specialist Design Flow and Methodology

    Intel Deutschland GmbH

    Senior Specialist for flow and methodology of digital implementation at Intel Deutschland GmbH

  • 7 Jahre und 8 Monate, Juli 2003 - Feb. 2011

    Freelance ASIC/SoC Physical Design Consultant and Engineer

    Alessandro Uber

    Professional design services in the field of VLSI design. Covering all the tasks required for the design closure of such integrated circuits. Focused on physical timing closure issues.

  • 3 Jahre, Juli 2000 - Juni 2003

    Application Engineer

    Magma Design Automation

    Customer support and training on EDA tools sold by Magma Design Automation

  • 7 Monate, Dez. 1999 - Juni 2000

    ASIC Design Engineer

    Avnet

    ASIC design and simulation, design for testability, logic synthesis, Verilog and VHDL coding

  • 2 Jahre und 2 Monate, Nov. 1997 - Dez. 1999

    Consulting Engineer

    Accent

    Design and implementation of digital ASIC designs from RTL coding to layout verification.

Ausbildung von Alessandro Uber

  • 6 Jahre und 3 Monate, Okt. 1989 - Dez. 1995

    Electronic engineering

    Università degli studi di Genova

    Microelectronics

Sprachen

  • Englisch

    Fließend

  • Italienisch

    Muttersprache

  • Deutsch

    Fließend

Interessen

Multi-User Dungeon (MUD) authoring
movies
fantasy books
free-climbing.

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