Min-An Chao

Angestellt, Expert ASIC Development, Bosch Sensortec GmbH

Munich, Deutschland

Fähigkeiten und Kenntnisse

ASIC PLD FPGA Digital Logic Design
Verilog VHDL
C/C++
System on Chip
DSP
Digital signal processing
Digital Signal Processing
Microprocessor
Mobile communication
Algorithm Development
Digital baseband system
Firmware
WiMAX
LTE
Digital IC integration
Verilog
ASIC
FPGA
SystemVerilog
Python-Programmierung
Computer Vision
Hardware in the Loop Simulation
Simulink
Mixed-Signal Circuit Design

Werdegang

Berufserfahrung von Min-An Chao

  • Bis heute 11 Monate, seit Juli 2023

    Expert ASIC Development

    Bosch Sensortec GmbH
  • 1 Jahr und 1 Monat, Juni 2022 - Juni 2023

    Senior Digital Design Engineer

    Inova Semiconductors GmbH
  • 2 Jahre und 2 Monate, Apr. 2020 - Mai 2022

    Senior Embedded Software Engineer in Control

    Blickfeld GmbH
  • 1 Jahr und 11 Monate, Jan. 2018 - Nov. 2019

    Werkstudent

    Intel Deutschland GmbH

    Machine learning related projects in autonomous driving

  • 4 Jahre und 1 Monat, Juni 2013 - Juni 2017

    Senior ASIC design engineer

    Mediatek

    Subgroup leader | Project: 2nd LTE-A/LTE-U modem series (Helio X20, P20, X30) - Led a subgroup of 4, responsible for baseband demodulator Group leader | Project: 1st automotive radar sensor project (with US site) - Led a group of 5, responsible for radar signal processor Digital ASIC designer | Project: 1st NB-IoT project (with Finland site) - Supported Viterbi decoder design

  • 2 Jahre und 8 Monate, Nov. 2010 - Juni 2013

    ASIC design engineer

    Mediatek

    Digital ASIC designer | Project: 1st LTE/LTE-A modem chipset (Helio P10, X10) - Contributed in LTE digital baseband team, from fixed-point algorithm, DSP architecture planning, firmware & RTL implementation & verification, in charge of outer receiver and frequency synchronization

Ausbildung von Min-An Chao

  • 2 Jahre und 5 Monate, Okt. 2017 - Feb. 2020

    Informatik/ Computer Science

    Technische Universität München

  • 1 Jahr und 10 Monate, Sep. 2008 - Juni 2010

    Electronics Engineering

    National Taiwan University

    - Overall GPA: 4.00/4.00 - Honour: Awarded “good design” at national IC design competition, twice, in 2008 & 2010 - Thesis: “Parallelized Particle Filter Design for CUDA Based Computing Platforms” supervised by Prof. Dr. An-Yeu Wu, IEEE fellow

  • 3 Jahre und 10 Monate, Sep. 2004 - Juni 2008

    Electrical Engineering

    National Taiwan University

    - Overall GPA: 3.80/4.00 - Honour: Presidential Award at Oct. 2007

Sprachen

  • Chinesisch

    Muttersprache

  • Englisch

    Fließend

  • Deutsch

    Gut

  • Japanisch

    Grundlagen

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