SABRISH MENON
Angestellt, Senior Physical Design Verification Engineer, Qualcomm CDMA Technologies
Bangalore, Indien
Über mich
> Having a total exp of 5+ years into Physical Verification/Sign-off for multiple projects on TSMC, INTEL & UMC processors using TSMC 7m, 16m & Intel specific 10nm,14nm, 22m & UMC 40m technology node. > Activities include DRC, FM, LVS, ERC, PERC Checks, DENSITY, LATCH- UP, ANTENNA, floorplan checks, soft-check, stamping conflict, scripting, cross-talk, RV & PDN fixes, EM, IR drop & ECO implementation. > Worked on multiple SOC/Sub-system/Blocks using Synopsys ICC, ICC-Il, IC Validator (ICV), Mentor Calibre,Cadence Innovus & Virtuoso tool for sign-off activity. > Led the team for couple of Tape-ins with Intel account, activities include driving the Block & Subsystem level sign-off checks, managing resources & assigning work to team members to delivering the GDS for Tape-in.
Werdegang
Berufserfahrung von SABRISH MENON
Bis heute 4 Jahre und 7 Monate, seit Nov. 2019
Senior Physical Design Verification Engineer
Qualcomm CDMA Technologies
- Certified ASIC Engineer with 5+ Years of experience as Physical Verification Engineer. - Hands on experience in EDA tool- ICC II, Innovus, IC Validator, IC Workbench, Mentor Calibre - Proficient in using INNOVUS/ICC II tool to fix DRC, LVS, DFM, Antenna, Softcheck, ERC, Crosstalk, EM, IR drop & ECO implementation. - Tech nodes worked on 4nm, 5nm, 7nm, 10nm, 14nm of Foundries like TSMC, Samsung & Intel. - Hands on experience in Floorplan, Placement, congestion removal, Routing & signoff activities.