Sujoy Paul
Angestellt, Chip Design R&D Engineer, II-VI Incorporated
Zurich, Schweiz
Werdegang
Berufserfahrung von Sujoy Paul
Bis heute 6 Jahre und 11 Monate, seit Aug. 2017
Chip Design R&D Engineer
II-VI Incorporated
Design and develop GaAs-based VCSEL for high volume applications. Engaged in chip design, process development, testing and implementation of new VCSEL generations. Leading own and contributing to related projects. Plan, execute & monitor the key process development tasks in close collaboration with the manufacturing team. Verify and document the product compliance with internal and customer specs, Communicate results and project status inside and outside organization.
5 Jahre und 6 Monate, Jan. 2012 - Juni 2017
Research Scientist
TU Darmstadt
Worked in BMBF funded technology transfer project which include companies like ADVA, VERTILAS etc. Received best paper award in Microoptics conference'15 held in Fukuoka, Japan. Received Travel Grant to attend Microoptics conference'15 in Fukuoka, and in SPIE Photonics West Conference'17 held in San Francisco, USA. Organized Europe's biggest event on VCSEL: 'European VCSEL day 2016'', chaired the seesion 'Optical Communication using VCSEL'.
3 Jahre, März 2006 - Feb. 2009
Lecturer
American International University Bangladesh
Ausbildung von Sujoy Paul
5 Jahre und 6 Monate, Jan. 2012 - Juni 2017
Electrical Engineering (Photonics and Optical Communications)
TU Darmstadt
Photonics, MEMS, VCSEL, Optical filters, Microfabrication, Optical measurements
2 Jahre und 6 Monate, März 2009 - Aug. 2011
Microelectronics
University of Ulm
Advanced Optical Communication System, MMIC Design, Microwave Engineering, RF System and ICs, Communication Engineering, Analog CMOS Circuit Design (with project), Compound Semiconductor, VHDL etc.
Sprachen
Englisch
Fließend
Deutsch
Gut
Französisch
Grundlagen
Bangla
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