TW Huang
Angestellt, Principal Digital Verification Engineer, Dialog Semiconductor
Hsinchu, Taiwan
Über mich
Design Verification Engineer with 10+ years of experience handling various SoC projects. A versatile, bilingual team player who can work in fast-paced and multi-cultural environments. Proficient in both high & low-level programming languages with excellent debugging skills.
Werdegang
Berufserfahrung von TW Huang
Bis heute 9 Jahre, seit Juni 2015
Principal Digital Verification Engineer
Dialog Semiconductor
• Obtain high coverage for digital control functions in PMIC/GreenPAK projects • Cooperate with teams in different countries in various projects • Upgrade the verification flow by implementing UVM & Formal tests • Extend verification on A/D interface behavior by using AMS & analog models • Accelerate project development by supporting other teams (Analog/AE/TE)
• Catch several system-level design issues in various HDD controller SoC projects • Transform sub-system & chip level testbench from VMM to UVM • Cooperate with US designers & DV team to verify SATA & PCIe functions • Improve project migration efficiency by building a Perl utility (translate C lib to SV)
1 Jahr und 3 Monate, Dez. 2010 - Feb. 2012
Design Verification Engineer
Mediatek
• Developed test plan to verify various designs for high-end smartphone ICs • Built and improved functional tests to reach high coverage before tape-outs • Trained and mastered various verification techniques such as VMM, Formal, SVA • Achieved >99% coverage for AVS, SPI, aux ADC control designs
• Worked in product development group to assist in generating, integrating, and improving test programs used for silicon development. • Learned the processes and techniques of testing CPUs by running tests, debugging issues, leading test code reviews, and documenting topics.
4 Monate, Mai 2007 - Aug. 2007
Engineering Intern
AREVA T&D
Ausbildung von TW Huang
2 Jahre und 5 Monate, Aug. 2007 - Dez. 2009
Electrical and Computer Engineering
The University of Texas at Austin
2 Jahre und 10 Monate, Sep. 2003 - Juni 2006
Electrical Engineering
University of Washington
Dean's List for Spring quarter 2004 and all quarters in 2005-2006
3 Jahre und 3 Monate, Mai 2000 - Juli 2003
Computer Engineering
Temasek Polytechnic
Director’s List for all three years
Sprachen
Englisch
Fließend
Chinesisch
Muttersprache
Japanisch
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