Umair Razzaq

Angestellt, Digital ASIC Design Engineer, Advantest Europe GmbH

Sindelfingen, Deutschland

Fähigkeiten und Kenntnisse

FPGA programming
VHDL
Verilog
Digital System Design
Digital Signal processing
Embedded Systems
Communication Electronics
Matlab
C/C++
SystemC
Python & PyQt
Visual Basic
Java
Xilinx ISE
ModelSim
Eclipse
ARM Cortex processor
CAN Bus
digitale Bildverarbeitung

Werdegang

Berufserfahrung von Umair Razzaq

  • Bis heute 9 Jahre und 10 Monate, seit Aug. 2014

    Digital ASIC Design Engineer

    Advantest Europe GmbH
  • 1 Jahr und 7 Monate, Apr. 2012 - Okt. 2013

    Research Student

    TU München

    Protocol layer interface implementation between a CAN virtualization wrapper for multi-core Virtual Machines and the Philips SJA 1000 CAN controller. Initializes the CAN controller and manages the data transfers. Implementation of Fault Injector on Actel’s SmartFusion customizable SoC evaluation kit. The fault injector, implemented on ProASIC3 FPGA, is used to inject erroneous clock and voltage spikes to an encryption engine.

  • 2 Monate, März 2012 - Apr. 2012

    Internee

    Linear Technology Munich

    Worked on the project “Emulation of Super Caps using programmable power supply”. The power supply was controlled over GPIB interface using SCPI commands. The project was developed in Eclipse, programmed in Python, while GUI was designed in PyQt library.

  • 4 Jahre und 4 Monate, Juni 2007 - Sep. 2011

    Design Engineer

    Advanced Engineering Reseach Organization(AERO)

    Design and implementation of Radar’s DSP Processor on FPGAs. The Algorithms include high order FIR filters, adaptive thresholding and sorting algorithms Design and development of signal processing algorithms Simulation and testing of each algorithm using Matlab Floating point and fixed point conversion of algorithms in C Synthesis using Xinlinx ISE and implementation on Virtex-IV FPGA Development and testing of FPGA cores for PCI, ADC and SRAM interfaces. High speed data acquisition system design.

  • 9 Monate, Aug. 2006 - Apr. 2007

    Trainee Engineer

    AndOr Logic

    On research based industry project; design and implementation of software and hardware for “E1 network analyzer” Firmware development using Verilog HDL, ANSI C and Microsoft Visual C++ Implemented on Spartan-3 FPGA with ATMEL microcontroller (ARM7), interfaced with computer via LAN which acts as control and command center.

  • 2 Monate, Aug. 2006 - Sep. 2006

    Intern

    Siemens Pakistan

    Worked in Communication Division (Special Systems) on TETRA communication system, Emergency Call Radio System design and Testing of PCB boards

Ausbildung von Umair Razzaq

  • 2 Jahre und 1 Monat, Okt. 2011 - Okt. 2013

    Communication Electronics

    Technische Universität München

    Digital IC design, HW SW Codesign, SoC Solutions in Networking, High Speed Digital CMOS circuits, Electronic Design Automation (EDA)

  • 3 Jahre und 9 Monate, Okt. 2003 - Juni 2007

    Computer Engineering

    National University of Science and Technology

    Digital Signal Processing, Digital System Design, Computer System Architecture, Digital Image Processing, Operating Systems

Sprachen

  • Englisch

    Fließend

  • Deutsch

    Gut

Interessen

Table Tennis
Hiking
Travelling

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