Vidwath Paramesh
Angestellt, FPGA Entwicklungs Ingenieur, iSyst Intelligente Systeme GmbH
Nuremberg, Deutschland
Werdegang
Berufserfahrung von Vidwath Paramesh
Department: Spatial Light Modulators (SLM) Group Tasks: Analyse previously designed DAC for resolution greater than 8 bits Provide alternative design methodologies for higher resolution DAC Documentation of the results obtained
Department: R&D- Spatial Light Modulators (SLM) group Title: CMOS design of Digital to Analog converters (DAC) for active matrix Spatial Light Modulator applications Tasks: Design of low power, high speed operational amplifiers for DAC’s Schematic design of 4 different DAC topologies Comparison of DAC topologies through Monte Carlo and area Layout design and extraction for the principle with very low power consumption and low area Assessment of suitability for SLM ASICs
Department: Electronic components of Micro and Nano technology Title: Analog design of Linear Voltage Controlled Oscillator (VCO) Tasks: Design of Current starved ring oscillator in X-FAB 180nm technology Schematic design of an Operational amplifier Monte Carlo and PVT analysis for linearity deviation of VCO
Ausbildung von Vidwath Paramesh
3 Jahre und 1 Monat, Okt. 2015 - Okt. 2018
Micro and Nano Systems
TU Chemnitz
Integrated Circuit Design, Advanced Integrated Circuit Technology, Micro and Nano devices, Automotive Sensor systems, Microsystem Design, Semiconductor Physics, Materials in micro and nano systems, Technologies for micro and nano systems, Power semiconductor devices
Sprachen
Englisch
Fließend
Deutsch
Gut