AJAY MISHRA
Angestellt, ASIC/FPGA Engineer - 2A, Ciena
Bengaluru, Indien
Über mich
• About 6 years of semiconductor field experience in Frontend Design, right from requirements gathering to final IP delivery stage • RTL Coding/Integration skills in Verilog, VHDL • Domain knowledge/expertise in fields of FPGA/ASIC based solutions • Good debugging skills for faster error detection at early stage of designing • A good team player with quick learning capabilities
Werdegang
Berufserfahrung von AJAY MISHRA
Bis heute 2 Jahre und 10 Monate, seit Sep. 2021
ASIC/FPGA Engineer - 2A
Ciena
• About 6 years of semiconductor field experience in Frontend Design, right from requirements gathering to final IP delivery stage • RTL Coding/Integration skills in Verilog, VHDL • Domain knowledge/expertise in fields of FPGA/ASIC based solutions • Good debugging skills for faster error detection at early stage of designing • A good team player with quick learning capabilities
1 Jahr und 2 Monate, Juli 2020 - Aug. 2021
Senior Engineer-Hardware Design
Mistral Solutions Pvt. Ltd.
2 Jahre und 10 Monate, Sep. 2017 - Juni 2020
Design Engineer
Bit Mapper Integration Technologies Pvt. Ltd.
Ausbildung von AJAY MISHRA
4 Jahre und 2 Monate, Mai 2011 - Juni 2015
Bachelor of Engineering (B.E.): Electronics & Communication Engineering
Gujarat Technological University
Sprachen
Englisch
Fließend