Ehsan Sabour
Angestellt, Hardware/FPGA Design Engineer, HEXOSYS
Kuala Lumpur, Malaysia
Werdegang
Berufserfahrung von Ehsan Sabour
Bis heute 6 Jahre und 10 Monate, seit Sep. 2017
Hardware/FPGA Design Engineer
HEXOSYS
Design, Implementation and Verification of Serial Attached SCSI (SAS) and SATA Subsystems.
3 Jahre und 5 Monate, Apr. 2014 - Aug. 2017
FPGA Design Engineer
ArtaVision
Design and Implementation of Digital Signal Processing algorithms. Design and Implementation of FPGA interfaces like high rate ADC and DAC, DDR3, SDRAM, SRAM, parallel low rate ADCs. Design and Implementation of a MAC Layer of 1G Ethernet. Hardware Software Co-simulation using Xilinx System Generator and MATLAB. Optimizing FPGA code to minimize resources and maximize clock speed.
6 Jahre und 10 Monate, Juni 2007 - März 2014
FPGA Design Engineer
EBK
Implementation of Digital Modulator and Demodulators in FPGA. Design and Implementation of Turbo and Convolutional Decoders in FPGA. Implementation of Digital Signal Processing algorithms in FPGA.
Ausbildung von Ehsan Sabour
3 Jahre und 1 Monat, Sep. 2007 - Sep. 2010
Digital Electronics
Shahid Beheshti University
Thesis Title: Design and Implementation of Turbo Decoder for DVB-RCS Standard. Partial Configuration on ML402 Xilinx Evaluation Board. Implementation of a Simple Pong Game. Experience in Xilinx, Altera and Actel FPGAs.
5 Jahre und 1 Monat, Sep. 2002 - Sep. 2007
Electrical Engineering
Khaje Nasir University of Technology