Ing. Haradipkumar Patel

Bis 2018, Engineering Intern / Master Thesis, Renesas Electronics Europe GmbH

Abschluss: Master of Science, Universität Duisburg-Essen

Essen, Deutschland

Fähigkeiten und Kenntnisse

Embedded Systems
FPGA Design
Verilog Vhdl
C (programming language)
Python
Programmable Logic Controllers (PLC) / Automation
Electronics
Microsoft Office
Microcontroller
FPGA-Programmierung
MS Windows
Circuit design
Test and Measurement
C++
Technical Support
Engineering
Software Development

Werdegang

Berufserfahrung von Haradipkumar Patel

  • Bis heute 2 Jahre und 10 Monate, seit Sep. 2021

    Software Developer

    Bertrandt Ingenieurbüro Köln

    • Support and responsibility for various process roles in software development. • Identification of optimization possibilities as well as errors and further development of customer-specific software solutions. • Design of software tests in the test environment including modifications of the simulation environment • knowledge of software testing methods, using software testing tools (e.g. dSPACE, Simulink) and model-based software development (e.g. Matlab, Simulink, Targetlink)

  • Bis heute 5 Jahre und 4 Monate, seit März 2019

    Application Engineer

    contest engineering

    • Software development • Python environment for data processing and data analysis. • Experience with EDA software to adapt standard circuits for special applications. • Selection of electronic components according to the required application performance parameters and conditions. • Knowledge of Embedded IoT solutions and related network protocols. • Rapid prototyping of circuits for evaluation, improvement, and testing of various sensors. • Linux environment for local applications solution

  • 10 Monate, März 2018 - Dez. 2018

    Engineering Intern / Master Thesis

    Renesas Electronics Europe GmbH

    • SIL and HIL for CNN processing on Renesas solutions • Python environment for reporting and data processing • Evaluation of different CNN network structures • Analysis of number formats and quantization errors on embedded hardware • Optimization of algorithm implementation for detection accuracy and stability • Experience with machine learning frameworks such as Caffe & TensorFlow • Programming in Python, C++ and C • Linux and window environments

  • 4 Monate, Sep. 2017 - Dez. 2017

    Intern

    Forschungszentrum Jülich

    • Zedboard (FPGA), Vivado Design Suite (Xilinx) • Hardware design, Software Development Kit (SDK) • Programming Languages: VHDL, Verilog, C, C++

  • 3 Monate, Sep. 2016 - Nov. 2016

    Project Engineer

    Arvato Systems
  • 1 Jahr, Sep. 2013 - Aug. 2014

    BSS Engineer

    3 Desire Networks(3DN)

    Working as a BSS Engineer in installation and commissioning

  • 7 Monate, Okt. 2013 - Apr. 2014

    Legal Intern

    Neo Creative Vision Technologies Private Limited

Ausbildung von Haradipkumar Patel

  • 3 Jahre und 8 Monate, Apr. 2015 - Nov. 2018

    Embedded Systems

    Universität Duisburg-Essen

  • 3 Jahre, Aug. 2010 - Juli 2013

    Electronics and Communication Engineering

    Gujarat Technological University(GTU)

  • 2 Jahre und 9 Monate, Aug. 2007 - Apr. 2010

    Electronics and Communication Engineering

    Technical examination board(TEB)

Sprachen

  • Deutsch

    Gut

  • Englisch

    Fließend

  • Hindi

    -

  • Gujarati

    -

Interessen

Reading
Travel
Musik
Playing Cricket
Cooking
visiting new palce
listing music
Photography

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