Syed Sohaib Ahmad

Designed and verified 13 bit SAR ADC on Silterra 130nm technology Designed and verified Trans-impedance amplifier and supporting circuitry for the SAR ADC Designed and verified PTAT circuit for temperature sensor application Designed and verified completed temperature sensor circuitry. IC test and characterization.

Intel Corporation (Seconded via Symmid), Apr 2020 to Sep 2020 Team lead for Audiolink IP Vidatronic (Seconded via Symmid), Feb 2020 to Mar 2020 BMOD vs schematic verification of LDO and switch capacitor DC-DC buck-boost converters Intel Corporation (Seconded via Symmid), Oct 2016 to Jan 2020 Verification of PLLs on Intel 10nm FinFet – PSG Verification of DLL in pOPIO Intel 10nm FinFet – MIG Verification of GPIO Buffer Intel 10nm FinFet – MIG Verification of GPIO Buffer Intel 14nm FinFet – MIG

IEEE 802.11 n Transceiver on GF 55nm LPx 10 GHz VCO design with -89 dBc/Hz phase noise for PLL (integration bandwidth from 10kHz to 20MHz, -89dBc/Hz at 100KHz offset) 10 GHz PLL with 0.32° (degree) phase noise 4.8 GHz Calibration PLL and 4 GHz Clock Generation PLL 20 MHz VGA & 5th order Chebyshev Filter design (MFB topology) 12 Bit SAR ADC on Global Foundry 55nm LPx Porting Microchip TSMC 65nm 12-bit SAR ADC to GF 55nm LPx Achieved 12-bit matching in DAC Increasing sampling rate from 2MSPS to 5MSPS

Delivered an IP Telephony system comprising of 16 PSTN trunks, 40+ internal extensions using Grandstream GXE-502x All-In-One IP-PBX and GXW 410x Series IP Analog Gateway. Setup 3CX software PBX on Microsoft Windows Server2003 and interfaced PSTN trunks using Grandstream GXW 410x Series IP Analog Gateway and Enterprise IP phones. Worked on the interoperability between ZTE and Grandstream products Troubleshooting VOIP calls, acquired and analyzed data packets captured using Wireshark

Power Electronic Design Solid State Devices HDL for Programmable Logic with Project Instrumentation and Measurement with Project VLSI Design DSP Mobile Communications RF Microelectronics with Project MSc Project Title: "Reconfigurable ESR Instrument Using FPGA"