Ing. Yash Pathak

Bis 2018, Electronics and Communication Engineering, Dharmsinh Desai University

Vadodara, Indien

Fähigkeiten und Kenntnisse

ASIC PLD FPGA Digital Logic Design
Simulation Program with Integrated Circuits Emphas
NI Multisim
Cadence Virtuoso
Verilog VHDL
The C Programming Language
Fortran
Object Oriented Programming
Python
C++
Java
Game Programming
Perl
MatLab
LabVIEW
Scilab
Analog Circuits
Linux
Material Science
Embedded Systems
Microcontroller
Intel-Core-Mikroarchitektur
IEEE 802.3
IEEE 802.4
IEEE 802.5
IEEE 802.11
Wireless Communication
Digital image processing
Quantum mechanics
Infrared spectroscopy
UV / Vis spectroscopy
Atomic force microscopy
X-Ray Diffraction Spectroscopy
Gonioreflectometer
PLC Programming
Programmable Logic Controller
CAD
Dynamic Light Scattering
Gas Chromatography-Mass Spectrometer
Ion Chromatography
Langmuir Blodgett Film balance and Surface Potenti
GNU Make
EMV-Messtechnik
Engineering
Verilog

Werdegang

Berufserfahrung von Yash Pathak

  • Bis heute 6 Jahre und 1 Monat, seit Mai 2018

    Engineer

    SCHOTT Glass India Pvt. Ltd.

  • 3 Monate, Mai 2017 - Juli 2017

    Summer Trainee

    Larsen & Toubro Electrical and Automation Division

Ausbildung von Yash Pathak

  • 1 Jahr und 1 Monat, Nov. 2020 - Nov. 2021

    Nanobiotechnology

    Technische Universität Kaiserslautern

  • 3 Jahre und 10 Monate, Aug. 2014 - Mai 2018

    Electronics and Communication Engineering

    Dharmsinh Desai University

Sprachen

  • Englisch

    Fließend

  • Französisch

    Grundlagen

  • Deutsch

    Gut

  • Hindi

    -

Interessen

Photography
Sports
Condensed Matter Physics

XING Mitglieder mit ähnlichen Profilangaben

Harald Netzer

Embedded Software Developer

Dornbirn

Preeta Katiyar

Microelectronics

Aschaffenburg

Christos Fontounasios

Associate Application Engineer - PCB Solutions

Feldkirchen, Munich, Germany

Srijeeta Sen

System Manager

Hildesheim

Pavel Laptev

Electronics Engineer

Moscow

Mahdi Shirazi

IT Engineer

Tehran

Jagadeesh Krovi

Electronics Engineer (FPGA)

Freiburg

Vishnu V Sunderlal

Hardware Layout Engineer

Munich

Alexander Grathwohl

Doktorand

Ulm

Muhammad Adil Saeed

Executive Assistant

Islamabad

Ramazan Esgin

Fpga engineer

Göttingen

Mohamed Hamouda

Senior Project Manager

Munich

Rachna Jani

Design & Verification Engineer

Ingolstadt

Adeel Zahir Shah

Freiberufliche Projekte

München

Vishwanath Prakash Hiremath

Information and Communication Engineering

Hamburg

Arvind Anche

Instrumentation and Electronics

Munich

Michael Brysch

Senior Principal Field Applications Engineer

Duisburg/München

Ganesh Chandrasekar

Senior VLSI Engineer

Bangalore

Muhammad Taimur Nasim

Hardware Engineer

Celle

Krishna Prasad M

Smart Systems

Mannheim

21 Mio. XING Mitglieder, von A bis Z

Nachname:

ABCDEFGHIJKLMNOP
QRSTUVWXYZ