Arun sattanathan Gothandaraman

Abschluss: MSc, Technische Universität München

Munich, Deutschland

Fähigkeiten und Kenntnisse

VHDL Development
Hardware Security
Digital Circuit Design
Matlab
simulink
C
C++
Channel coding
Testing Digital Circuits
FSO
SystemC
Altera Quartus II
Xilinx ISE
Modelsim
SignalTap II
Embedded Systems
Microcontroller
Embedded Software
FPGA-Programmierung
ASIC-Technik
Firmwarentwicklung
Eclipse
DPA

Werdegang

Berufserfahrung von Arun sattanathan Gothandaraman

  • Bis heute 8 Jahre und 2 Monate, seit Apr. 2016

    Software Engineer

    Arccore AB

  • 8 Monate, Apr. 2015 - Nov. 2015

    Master thesis Student

    Deutsches Zentrum für Luft- und Raumfahrt e.V.

    “ Firmware development and testing for Optical Communication transceivers” A. TECHNICAL : Transceiver for Free space optical Communication,Channel Coding (RS code,Viterbi algorithm etc),Interleaving (2d / 3d),PLL. B. DIGITAL DESIGN : 1) IP ; 2) Memory Management ; 3) Bus : PCI ; 4) TOOLS USED : Altera Quartus II (13.1) Altera Quartus II (14.0 – Web edition) ,Modelsim,Signal TapII,Pin planner;5) BOARDS USED :Arria V , Cyclone IV

  • 9 Monate, Juli 2014 - März 2015

    Intern

    Technische Universität München - EI SEC

    (RESEARCH) THRESHOLD IMPLEMENTATION OF PRESENT (Light Cryptography) SUPERVISOR : Fabrizio De Santis , Research Scientist (TUM - SEC) Main Scope: Reducing the number of shares so that the size of the crypto module is reduced. Previous implementations uses 3 shares which is 3 times the size of the basic implementation. Key Ideas Implemented : Irregular number of shares (2 shares – 3 share),Reducing the size by storing just 2 shares

  • 8 Monate, Nov. 2013 - Juni 2014

    Intern

    Technische Universität München - EI SEC

    THRESHOLD IMPLEMENTATION OF AES - SUPERVISOR : Fabrizio De Santis , Research Scientist (TUM - SEC) A. TECHNICAL INSIGHT ABOUT : Side channel Analysis (DPA),Shamir’s secret sharing,Threshold Implementation ,Masking PLAINTEXT and KEY,Galois Field, Leakage Resistant B. DIGITAL DESIGN : 1) Low power design; 2) Designing to reduce the size ; 3)Testing the design : Simulation tool,Gate level /Whole design/ and Board Testing; 4)TOOLS USED : Xilinx (ISE v14.6),ISim;5) BOARDS USED : SPARTAN 3E , SPARTAN 6

  • 2 Jahre und 3 Monate, Juli 2011 - Sep. 2013

    Software Engineer

    UST Global

    1) Involved in all stages of Software Development Life Cycle (2)Have experience in programming Microcontroller (ARM based) 3)Created modules with RTOS (FreeRTOS , emBOS etc) for microcontrollers 4)Basic understanding about ARM programming in C and assembler(5)Implemented data structures (stack, queue etc) in C, C++(6)Hands on experience in Preparing Unit test cases, test specification and test documentation(7)Assigned tasks for a small team of 5 members on both daily and weekly basis

Ausbildung von Arun sattanathan Gothandaraman

  • 2 Jahre und 1 Monat, Okt. 2013 - Okt. 2015

    Masters in Communication Engineering (MSCE)

    Technische Universität München

    Digital Design (VHDL), Cryptography(AES,PRESENT),Hardware security (Thresholding, Masking, Shamir's sharing), Testing digital circuits, Channel coding etc.

  • 4 Jahre und 1 Monat, Mai 2007 - Mai 2011

    Electronics and Communication Engineering

    Anna University of Technology Tirunelveli

    VLSI, Embedded systems, Electronic Circuits, Electromagnetic Theory, Signal Processing

Sprachen

  • Englisch

    Fließend

  • Deutsch

    Gut

  • Tamil

    -

Interessen

Filmmaking
Music

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