Ing. Farooq Anwar Sheikh

is looking for freelance projects. 🔎

Angestellt, Senior Manager FPGA & IP DV, Rapid Silicon

Lahore, Pakistan

Über mich

I'm a design verification engineer working to better understand how different systems motivates and shapes integrated circuits. My expertise includes project design and management, data analysis and interpretation, and the development and implementation of research tools. I enjoy generating new ideas and devising feasible solutions to broadly relevant problems. My colleagues would describe me as a driven, resourceful individual who maintains a positive, proactive attitude when faced with adversity. Currently, I'm seeking opportunities that will allow me to develop and promote technologies that benefit our daily technology solutions. Specific fields of interest include ASIC, FPGA, and System Verilog (VHDL)

Fähigkeiten und Kenntnisse

Implementation
ASIC
FPGA
verilog
Simulation
Integrated circuit layout
MatLab
Software Engineering
Linux
C++
Python
VHDL
Tcl
cadence
Multicultural experience
multicultural awareness
ability to adapt within multicultural teams
International experience
Social Media
Computer Science
Computer Engineering
Entrepreneurial spirit
entrepreneurial thinking
sense of humor
cooperative
Professional
friendly manner
German language
English Language
Master's degree
willingness to travel
Business travel
C#
Design
Engineering
Simulink

Werdegang

Berufserfahrung von Farooq Anwar Sheikh

  • Bis heute 1 Jahr und 6 Monate, seit Dez. 2022

    Senior Manager FPGA & IP DV

    Rapid Silicon

    As part of the management, my responsibilities include: . Working with the team under the supervision of management to plan and direct the work of the department. • Managing different projects to gain perspective and understanding of the functioning of the organization. • Assisting upper management in setting performance goals, monitoring performance progress, and evaluating work output to optimize departmental functioning. • Preparing documentation and reports on departmental progress and policies.

  • 6 Monate, Juli 2022 - Dez. 2022

    FPGA Verification Engineer

    Synopsys

    o Building a reference design SOC system for ARC processor IP o Mapping the SOC to FPGA-based platforms like HAPS/ZeBu (Need FPGA development flow knowledge & experience) o Developing & running SW tests on HAPS/ZeBu to validation ARC processor function/performance/power(Basic embedded programming & SW skillset) Job Requirements: o Working with embedded processors or processor-based systems

  • 1 Jahr, Jan. 2022 - Dez. 2022

    Digital ASIC/FPGA Engineer

    IMEC

    RTL implementation (mainly in (System-)Verilog, but VHDL is also possible) and verification (in System-Verilog) of components for a Digital Baseband for a radio system. The specification of the to-be-implemented components is usually in Matlab / Python.

  • 6 Jahre und 5 Monate, Feb. 2016 - Juni 2022

    Design Verification Engineer

    Elmos Semiconductor AG

    - RTL implementation in VHDL for AIRBAG SYSTEM specifically SPI, JTAG, Safing Agent, Configuration, Supply and GPO. ASIC design on TSMC Technology. - Hardware Design and implementation in System Verilog for “USPA hardware” specifically ADA (Analogue to Digital converter) and OTP memory. ASIC design on ELMOS Technology and prototyping in FPGA. - Implementation Of UVM flow in System Verilog.

  • 2012 - 2016

    Software Developer

    dSPACE GmbH

    - Developed SOME/IP- Adapter application in c for Linux firmware. The platform consists of Xilinx FPGA, with Dspace processor and Debian operating system. - Developed and implemented Matlab Models generator for Some/IP-Service Discovery blocks. - Developed in c-sharp the test code generator. To make the test scripts recongurable for future changes, xslt based scripts were used. the csharp code converted excel sheets to scripts based on xslt codes. The tool generated Matlab and Python codes

  • 5 Monate, Apr. 2012 - Aug. 2012

    Verification Engineer

    Infineon Technologies

    - Verication of C65,L90 I/O-Pads and oscillator in Avenue with Cadence Virtuoso, HSIM and Pspice test benches. - Automated the verication plans using Linux shell scripts and verication tools. The reports were generated in pdf by help of latex scripts.

Ausbildung von Farooq Anwar Sheikh

  • 2008 - 2010

    DNA-Chip-Technologie

    Faculty of Engineering (LTH), Lund University

  • 2002 - 2006

    Electrical and Computer Engineering

    COMSATS Institute of Information Technology (CIIT), Islamabad

Sprachen

  • Englisch

    Muttersprache

  • Deutsch

    Gut

  • Arabisch

    Grundlagen

  • Urdu Native Knowledge

    -

  • Punjabi Good Knowledge

    -

Interessen

Tech Geek. Foodie. Gaming. Travelling. Cars.

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