Leela Thimmaiah

Development and integration of verification environment components utilizing UVM/SystemVerilog Testbench Development for verification modules Creating Verification/Test plans from Functional Specifications Generate directed and constrained random tests. Development, simulation and debug of UVM based test cases Analyze and debug of failed regression testcases for the whole testbench Create & analyze coverage model Enhance testbench/test to increase coverage

Development of SV testbenches Development of feature based verification plan (Vplan) Constraint random verification Metric-Driven Verification (MDV) SystemVerilog Assertions (SVA)

Design & performance analysis of a memory request scheduler based on Parallelism-Aware Batch Scheduling algorithm for GDDR5 memory controller Development of a sophisticated and automated verification infrastructure (Multiple Test Scenarios, Layered Sequences, Drivers and Monitors) using System Verilog based OVM/UVM Executing test/coverage plans and verifying correctness of the design Constrained random stimulus generation along with functional coverage and assertion-based verification (SVA)

Power analysis and Optimizations of MSP430 CPU, setup of synthesis and layout scripts. Analysis of synthesis issues using Conformal LEC and Gate level simulator of testcases, Analysis of synthesis results for different adder structures and RTL optimizations to increase resource sharing. Estimation and analysis of energy and performance of CPU for coremark and other benchmarks like Whetstone, Dhrystone, etc and different testcases/applications.

Modeling of high power MOSFETs Definition of component libraries, system simulations, developing testbenches in order to model the behavior of the high power device CoolMOS™. All the simulations and test benches are done in ADS (Agilent Technologies). The model is also tested in different simulators like Spectre (cadence) and Simetrix (PSpice). Simulations are compared with the measurement data. Every model is tuned and optimized in order to obtain the best results.

Operation & Maintenance of the core Network for desired SLA. Defining new routes & Augmentation of POIs, SS7 signaling link definition, Routing case analysis. Monitoring core network utilization and reporting variations. Understanding the GSM call processing and analyzing SIP,BICC & ISUP (IP based protocols) messages. Daily checks of POI utilizations of all the operators connected to MSC. Control Utilization on all POIs by raising plan for the new augmentation with all partners

Hardware Description Languages (Verilog,System Verilog,VHDL), Verification Techniques: Formal Verification, OVM/UVM, SVA, CDV, Design for testability (DFT). Advanced digital IC/Mixed-Signal circuit design.

Mobile Communications, Digital/Analog Communications, Satellite Communications, Digital Signal Processing