Taskeen Zaidi

Development of portable stimuli for functional verification of a Generic Timer Module. Goal is to test & develop a verification framework for generating portable stimuli for functional verification , which is portable between different integration levels i:e, SoC and Subsystem level ,portable among different products of the same DUT as well as RTL simulation and Emulation using Cadence Perspec System Verifier.

Tasked to develop a sufficient enough model for EVADC module so as to get better coverage and test scenarios as compared to current directed test case based methodology used for SoC/Sub-system verification. Also to make the model independent of the underlying DUT so as to increase re-usability among different variants of controllers of the same family.

NSS Core services including load management. Release and Change management activities on ALU CDMA NSS N/w. Integration and Acceptance testing of ATCA RNC’s. Integration of MMCv4, UTP and MTP traffic processors..

Advanced Integrated Circuit design, Microprocessor Systems , Circuit Building blocks for Communication Systems . HDL:Verilog & VHDL, HDL Lab, Advanced Integrated circuit design Lab, Project Seminar Design for testability, Digital Signal Processing

Electrical engineering , Semiconductor Devices & circuits, Analog integrated Circuits, Signal & Systems, VLSI Technology & Design, Digital Signal Processing