WALID BOUKRA
Angestellt, FPGA Design and Verification Engineer, LLR (CNRS / Ecole Polytechnique de Paris)
Montréal, Kanada
Werdegang
Berufserfahrung von WALID BOUKRA
Bis heute 2 Jahre und 3 Monate, seit Apr. 2022
FPGA Design and Verification Engineer
LLR (CNRS / Ecole Polytechnique de Paris)
LLR is a CNRS laboratory located at Ecole Polytechnique of Paris and is currently taking part in the CMS experiment, which is taking place at CERN, in Switzerland. My role is to design and verify the firmware which will be implemented in an FPGA to process the data coming from the CMS detector, which is located at a certain point of the LHC (Large Hadron Collider).
7 Monate, Feb. 2018 - Aug. 2018
FPGA and ASIC design engineer
MDA Space Missions
Ausbildung von WALID BOUKRA
5 Jahre und 4 Monate, Sep. 2012 - Dez. 2017
Microelectronics engineering
Université du Québec à Montréal (UQAM)
FPGA and ASIC design and verification using VHDL and Verilog, Embedded systems programming using C, Digital signal processing
Sprachen
Englisch
Muttersprache
Französisch
Muttersprache
Deutsch
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