Dipl.-Ing. Daniel Petreus

With over 23 years of experience on FPGA technologies, I provide FPGA design, integration, implementation and validation contracting services for companies using FPGA technologies (complete front-end / back-end flow on AMD (XILINX), INTEL (ALTERA), Microchip FPGA technologies) or ASIC technologies (RTL Design). Clients portfolio: INTEL Corporation, ALCATEL-LUCENT, ERICSSON, ST-ERICSON, ROCKWELL-COLLINS part of Collins Aerospace part of Raytheon Technologies, Duolog Technologies, etc...

FPGA - RTL (VHDL) design, integration, synthesis, implementation, STA, validation, verification, documentation (DO-254 project)

Provide FPGA - RTL (VHDL) design, integration, synthesis, implementation, STA, validation, verification and documentation services. EDA Tools: Vivado 2016.x, Questasim 10.5c, Integrity 10, Teraterm. HW : Xilinx ZCU102 FPGA Eval board and Quad Ethernet FMC FPGA: Zynq UltraScale+ MPSoC Implemented a Xilinx External FIFO Interface (EFI) from GEM3 port of the ZCU102 Eval Board. Integrated a Managed Ethernet Switch (MES) IP. Connected 2 x EthernetFMC HW modules to 8 x RGMII ports of the MES.

FPGA - RTL (VHDL) design, integration, synthesis, implementation, STA, validation, verification, documentation (DO-254 project)

Provide FPGA Design and Emulation services. Porting ASIC soft IP and hard IP into FPGA Technology. Working on Synopsis HAPS-62 platform with 2 Virtex 6 FPGAs. The purpose of my wok was to facilitate software testing on FPGA platform before ASIC tape out.

Part of the FPGA development team, provide front-end and back-end FPGA services for Alcatel - Lucent in Stuttgart, Germany, working on 2G/3G/4G technologies on Xilinx FPGA based platforms for Base Stations. In this role I am responsible for different tasks that are assigned to me anywhere during the FPGA design flow, starting from front-end RTL design and integration up to back-end process (synthesis, implementation, STA, bit file generation) and testing on different HW platforms in the FPGA laboratory.

Senior ASIC/FPGA design engineer consultant/freelancer for ST-ERICSSON (former Ericsson EMP), Nürnberg, Germany. I was part of an experienced ASIC/FPGA design team implementing the next generation of Broadband Mobile Wireless Communication prototypes and chipsets (HSPA Evo, Multicarrier and LTE) allowing for higher throughputs in mobile networks.

Senior ASIC/FPGA design engineer consultant/freelancer for ERICSSON Mobile Platforms, Nürnberg, Germany. I was part of an experienced ASIC/FPGA design team implementing the next generation of Broadband Mobile Wireless Communication prototypes and chipsets (HSPA Evo, Multicarrier and LTE) allowing for higher throughputs in mobile networks. Ericsson was the most advanced company showing end to end demos of HSPAevo and LTE prototypes in Barcelona “Mobile world congress” in 2008.

Senior ASIC/FPGA design engineer and 802.11 a/b/g/e/i/n MAC FPGA architect and team leader. Duolog provides Wireless Platforms, SoC Flow Automation Solutions and SoC Design Services to the wireless communication market. Founded in 1999, the company is headquartered in Dublin, Ireland with design offices in Galway, Ireland and Budapest Hungary. Main responsibilities: Coordinate, design and implement necessary changes to support 802.11e and 802.11i standards and handling customers additional requirements.

ASIC/FPGA verification engineer at NoBug Consulting SRL (see www.nobugconsulting.ro). NoBug delivers quality, high-performance ASIC and VLSI solutions for the multimedia, telecommunications, networking and computer industries. Main responsibilities: SOC testing.

ASIC/FPGA design engineer at Metar A.D.C. with Sistolic group (see www.sistolic.com). Sistolic is an ASIC/FPGA design service and also an Intellectual Property provider company. Sistolic is specialized in communications and high-speed network components. Main responsibilities: 802.11 MAC HW developer, RTL code design, testing and optimization for the ASIC/FPGA flow, training for customers.

ASIC/FPGA design engineer. Path1 developed the True Circuit technology that preserves the Quality of Service (QoS) for audio, video, telephony, and all other forms of real-time traffic flowing over standard Ethernet/IP computer networks. Path1 provides video routing products to merge broadcast and cable quality video transport with IP networks. Main responsibilities: RTL code design, testing and optimization for the ASIC/FPGA floflow, training for customers.

Master of Bussiness Administration

ASIC / FPGA technologies, Systems with open architectures

Computer Science, Mathematics, Phisics, Software Analyst.