Zheng Wang

Student, Multi-Processor Systems-on-Chip (MPSoC), UMIC, ISS, RWTH Aachen

München, Deutschland

Fähigkeiten und Kenntnisse

Computer engineering
CPU
ASIP
ASIC
DSP
FPGA
CGRA; Low power and reliable system; Parallel prog
IC Design; Electronics
Electromagnetics
Optics Skills: C
C++
OOP
Assembly
LISA
VHDL
Matlab
VBA
SystemC
GUI
Java
Perl
Linux
Linux kernel
Device drivers. Tools: QT
Eclipse
Kdevelop
Synopsys Processor Designer
Platform Architect
Design Compiler
PrimeTime
GNU
Modelsim
Xilinx ISE

Werdegang

Berufserfahrung von Zheng Wang

  • 8 Monate, März 2009 - Okt. 2009

    Diplomant

    Infineon Technologies AG, Munich

    Implement PFAIR Real-time Scheduling Algorithm on Linux OS for ARM Multiprocessor platform.

  • 7 Monate, Aug. 2008 - Feb. 2009

    Intern

    Institute for Integrated System, TU Munich

    Implement Fault Tolerant Processor Pipeline with ECC Protection on Leon3 processor.

  • 5 Monate, März 2008 - Juli 2008

    Working Student

    Infineon AG

    Program data processing tools for annual financial report and economical trend analysis.

  • 5 Monate, März 2007 - Juli 2007

    Thesis Student

    Advanced Photonics Materials and Devices Laboratory, SJTU

    Model optical wave in periodic layered media by transfer matrix method;

  • 2 Monate, Sep. 2006 - Okt. 2006

    Intern

    Bundesanstalt für Straßenwesen

    Take part in several measurement projects for German autobahns; Evaluate the result of measurement by internal data processing tools.

  • 7 Monate, Sep. 2005 - März 2006

    Intern

    Shanghai Yufeng Investment consulting Co.,ltd

    Responsible for working and living affairs of foreign students in Shanghai; Work as student leader to organize parties, travels and conferences

Ausbildung von Zheng Wang

  • Bis heute 13 Jahre und 10 Monate, seit Sep. 2010

    Multi-Processor Systems-on-Chip (MPSoC)

    UMIC, ISS, RWTH Aachen

    Application-specific Instruction-set Processor Design, High-level Synthesis, ASIC Design, Tools development for low power and reliable processor design flow.

  • 2 Jahre und 1 Monat, Okt. 2007 - Okt. 2009

    Communication Electronics

    Technische Universität München

    Communication technology; digital circuits design; computer architecture; embedded system

  • 4 Jahre und 11 Monate, Sep. 2002 - Juli 2007

    Physics

    Shanghai Jiaotong University

    Semiconductor physics; electronics; optics and photonics;

Sprachen

  • Chinesisch

    Muttersprache

  • Englisch

    Fließend

  • Deutsch

    Gut

Interessen

Basketball
football
tennis
table tennis
swimming
learning foreign languages
Chinese cuisine

21 Mio. XING Mitglieder, von A bis Z